Hybrid wafer dicing approach using laser scribing process based on an elliptical laser beam profile or a spatio-temporal controlled laser beam profile

ABSTRACT

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an elliptical or a spatio-temporal controlled laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

BACKGROUND

1) Field

Embodiments of the present invention pertain to the field of semiconductor processing and, in particular, to methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits thereon.

2) Description of Related Art

In semiconductor wafer processing, integrated circuits are formed on a wafer (also referred to as a substrate) composed of silicon or other semiconductor material. In general, layers of various materials which are either semiconducting, conducting or insulating are utilized to form the integrated circuits. These materials are doped, deposited and etched using various well-known processes to form integrated circuits. Each wafer is processed to form a large number of individual regions containing integrated circuits known as dice.

Following the integrated circuit formation process, the wafer is “diced” to separate the individual die from one another for packaging or for use in an unpackaged form within larger circuits. The two main techniques that are used for wafer dicing are scribing and sawing. With scribing, a diamond tipped scribe is moved across the wafer surface along pre-formed scribe lines. These scribe lines extend along the spaces between the dice. These spaces are commonly referred to as “streets.” The diamond scribe forms shallow scratches in the wafer surface along the streets. Upon the application of pressure, such as with a roller, the wafer separates along the scribe lines. The breaks in the wafer follow the crystal lattice structure of the wafer substrate. Scribing can be used for wafers that are about 10 mils (thousandths of an inch) or less in thickness. For thicker wafers, sawing is presently the preferred method for dicing.

With sawing, a diamond tipped saw rotating at high revolutions per minute contacts the wafer surface and saws the wafer along the streets. The wafer is mounted on a supporting member such as an adhesive film stretched across a film frame and the saw is repeatedly applied to both the vertical and horizontal streets. One problem with either scribing or sawing is that chips and gouges can form along the severed edges of the dice. In addition, cracks can form and propagate from the edges of the dice into the substrate and render the integrated circuit inoperative. Chipping and cracking are particularly a problem with scribing because only one side of a square or rectangular die can be scribed in the <110> direction of the crystalline structure. Consequently, cleaving of the other side of the die results in a jagged separation line. Because of chipping and cracking, additional spacing is required between the dice on the wafer to prevent damage to the integrated circuits, e.g., the chips and cracks are maintained at a distance from the actual integrated circuits. As a result of the spacing requirements, not as many dice can be formed on a standard sized wafer and wafer real estate that could otherwise be used for circuitry is wasted. The use of a saw exacerbates the waste of real estate on a semiconductor wafer. The blade of the saw is approximate 15 microns thick. As such, to insure that cracking and other damage surrounding the cut made by the saw does not harm the integrated circuits, three to five hundred microns often must separate the circuitry of each of the dice. Furthermore, after cutting, each die requires substantial cleaning to remove particles and other contaminants that result from the sawing process.

Plasma dicing has also been used, but may have limitations as well. For example, one limitation hampering implementation of plasma dicing may be cost. A standard lithography operation for patterning resist may render implementation cost prohibitive. Another limitation possibly hampering implementation of plasma dicing is that plasma processing of commonly encountered metals (e.g., copper) in dicing along streets can create production issues or throughput limits.

SUMMARY

Embodiments of the present invention include methods of, and apparatuses for, dicing semiconductor wafers.

In an embodiment, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an elliptical laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

In another embodiment, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a spatio-temporal controlled laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

In another embodiment, a system for dicing a semiconductor wafer having a plurality of integrated circuits includes a factory interface. The system also includes a laser scribe apparatus coupled with the factory interface and having a laser assembly configured to provide a laser beam having an elliptical profile or a spatio-temporal controlled profile. The system also includes a plasma etch chamber coupled with the factory interface.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a Flowchart representing operations in a method of dicing a semiconductor wafer including a plurality of integrated circuits, in accordance with an embodiment of the present invention.

FIG. 1B is a Flowchart representing operations in another method of dicing a semiconductor wafer including a plurality of integrated circuits, in accordance with an embodiment of the present invention.

FIG. 2A illustrates a cross-sectional view of a semiconductor wafer including a plurality of integrated circuits during performing of a method of dicing the semiconductor wafer, corresponding to operation 102A of the Flowchart of FIG. 1A or to operation 102B of the Flowchart of FIG. 1B, in accordance with an embodiment of the present invention.

FIG. 2B illustrates a cross-sectional view of a semiconductor wafer including a plurality of integrated circuits during performing of a method of dicing the semiconductor wafer, corresponding to operation 104A of the Flowchart of FIG. 1A or to operation 104B of the Flowchart of FIG. 1B, in accordance with an embodiment of the present invention.

FIG. 2C illustrates a cross-sectional view of a semiconductor wafer including a plurality of integrated circuits during performing of a method of dicing the semiconductor wafer, corresponding to operation 108A of the Flowchart of FIG. 1A or to operation 108B of the Flowchart of FIG. 1B, in accordance with an embodiment of the present invention.

FIG. 3A illustrates two possible pathways for elliptical beam profile generation, in accordance with an embodiment of the present invention.

FIG. 3B illustrates possible orientation of a generated elliptical beam, in accordance with an embodiment of the present invention.

FIG. 3C illustrates a comparison of scribing roughness for (i) a circular beam process versus (i) an elliptical beam process, in accordance with an embodiment of the present invention.

FIG. 4A illustrates a comparison of scribing roughness for (i) a circular beam process versus (ii) a flat-top beam process or (iii) an elliptical beam process, in accordance with an embodiment of the present invention.

FIG. 4B illustrates sidewall finishing for (i) a femtosecond laser, (ii) a picosecond laser and (iii) a temporally controlled laser, in accordance with an embodiment of the present invention.

FIG. 4C illustrates a laser scribing process including generation of a spatio-temporally controlled laser, in accordance with an embodiments of the present invention.

FIG. 5 illustrates the effects of using a laser pulse width in the femtosecond range, picoseconds range, and nanosecond range, in accordance with an embodiment of the present invention.

FIG. 6 illustrates a cross-sectional view of a stack of materials that may be used in a street region of a semiconductor wafer or substrate, in accordance with an embodiment of the present invention.

FIGS. 7A-7D illustrate cross-sectional views of various operations in a method of dicing a semiconductor wafer, in accordance with an embodiment of the present invention.

FIG. 8 illustrates a block diagram of a tool layout for laser and plasma dicing of wafers or substrates, in accordance with an embodiment of the present invention.

FIG. 9 illustrates a block diagram of an exemplary computer system, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits thereon, are described. In the following description, numerous specific details are set forth, such as various laser beam profile laser scribing approaches and plasma etching conditions and material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known aspects, such as integrated circuit fabrication, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

A hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch may be implemented for die singulation. The laser scribe process may be used to cleanly remove a mask layer, organic and inorganic dielectric layers, and device layers. The laser etch process may then be terminated upon exposure of, or partial etch of, the wafer or substrate. The plasma etch portion of the dicing process may then be employed to etch through the bulk of the wafer or substrate, such as through bulk single crystalline silicon, to yield die or chip singulation or dicing. More specifically, one or more embodiments are directed to implementing an elliptical profile laser beam laser scribing process or a spatio-temporal controlled profile laser beam laser scribing process for, e.g., dicing applications.

In a first aspect, elliptical laser beam generation is described for improving laser scribing processing in hybrid laser die singulation.

To provide context, hybrid technology combining laser scribing and plasma etching enables precise thin semiconducting device die cutting from a silicon (Si) wafer. Laser scribing is used to scribe the wafer surface to singulate the semiconducting device die by combining with a plasma etching process. The conventional laser has a Gaussian beam profile and peak area used for cutting the surface. The overlapping of laser spots during the scribing process, however, can cause the roughness change due to the overlapping phase of laser spots.

In accordance with an embodiment of the present invention, by using the elliptical laser spot instead of a regular circular shape, the generated laser beam profile can be used to achieve a fine roughness and narrow kerf width scribing. In addition, the sidewall may be rendered smoothly finished by focal depth change from a positional control of optics. In one embodiment, an elliptical laser beam is generated by a cylindrical lens and collimated laser beam unit. The focal length of lens determines the depth of focus and adjusts the numerical aperture for scribing process. Due to the throughput and precise dimension requirements, the proper specification of cylindrical lens and related collimated optics are selected. In one embodiment, the smoothness and roughness control of laser scribed die profile is critical for die singulation because the plasma etching process begins with the opening shape of scribed pattern on the wafer. In one or more embodiments, use of an elliptical laser beam improves the uniformity of wafer dicing processes and provides for high-quality productivity.

In a particular embodiment, as described in greater detail below, an elliptical laser beam is used to overlap the laser spots during the scribing process to achieve a level of smoothness and fine roughness for enabling a clean laser scribing and plasma etching dicing process. Advantages of such elliptical laser beam profile embodiments may include, but are not limited to, (1) precise scribing of the mask coating/device layers on the Si substrate, (2) ready control of the laser scribing profile and shape, (3) enablement of the roughness control of a scribed section on a Si substrate, (4) achievement of the smoothness of the sidewall of trench during the process and rendering of the three-dimensional smoothing effect for a scribed structure, and (5) production of a uniform and effective etching process. The uniform die singulation by plasma etching was achieved by the flattened and smoothly cut surface by a laser scribing process. One or more embodiments can apply to a laser machining process for improving the surface roughness of the finished product, e.g., the resulting dies.

In a second aspect, spatio-temporal laser profile control is described for improving laser scribing processing in hybrid laser dicing.

To provide contact, a hybrid laser scribing and plasma etching singulation process may be based on a femtosecond laser scribing and plasma etch hybrid technology for dicing wafers. A hybrid technology combining laser scribing and plasma etching enables the precise thin semiconducting device die cutting from a Si wafer. An ultra-short laser may be an essential part of the process for achieving the fine scribing of die streets to singulate wafers with a subsequent plasma etching process.

In accordance with an embodiment of the present invention, spatial and temporal control of the laser beam profile determines the smoothness and roughness of laser scribing process. For example, the scribing process in a hybrid dicing process has a primary purpose of opening the multiple layers on the top of the Si wafer and may be a critical preliminary process for a subsequent plasma etching process as a sequential process since the etching profile follows the opened shape of the wafer as formed by laser scribing.

In a particular embodiment, as described in greater detail below, the importance for spatial and temporal control of a laser beam is shown to affect the scribing/etching results of hybrid dicing processing. The spatial profile is controlled using a diffractive optical element or cylindrical lens unit and can be implemented to achieve fine roughness by generating flat-top or elliptical laser beam profiles. The temporal profile is controlled for smoothing the surface of a scribed wall by combining a micro- and macro-ripple profile due to the temporal profile variation. In an embodiment, advantages from both spatial and temporal control of a laser beam produces the synergetic advantageous effect on a scribing process. Such a combination of laser profile control can be used for refined die singulation, particularly when a next plasma etching process is implemented. The result can be high quality productivity.

Advantages of such spatio-temporal control embodiments may include, but are not limited to, (1) the ability to make precise scribing in the mask coating/device layers on the Si substrate, (2) ready control of the laser scribing profile and shape, (3) enablement of roughness control of a scribed section on a Si substrate, and (4) the incorporation of multiple beneficial effects during one scribing process. In an embodiment, the spatio-temporal control of a laser pulse provides for both sharp and smooth cutting results at the same time during the scribing process. In addition, the consecutive smoothing of the sidewall of the Si trench during the process can be implemented to enable a subsequent uniform and effective etching process. The uniform die cut by plasma etching may be achieved by the regularly flattened surface cut by laser scribing process. Embodiments described below may be applicable to a laser machining process for improving the surface roughness and sidewall smoothness of the singulated product.

To provide further general context, in a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch, a femtosecond laser may be applied to remove the mask and device layers on the dicing street until the silicon substrate is exposed. A plasma etch follows to separate dies. One quality item or issue pertains to the die sidewall smoothness. The die sidewall can have a scallop pattern both along the die thickness and along the laser scribing direction. The depth-wise scallop pattern may be a result of iterative Bosch etch processing. Typically, the roughness is at the sub-micron level. Horizontal scalloping along the laser scribing direction can be caused by an imperfect spot overlap and a non-uniform distribution of non-silicon materials (e.g., metals, dielectrics, etc.) on the dicing street. By comparison, the order of roughness for a horizontal type of scallop can be on the order of a few microns.

On the aspect of appearance, any imperfect opening of a mask layer can be inherited by the resulting sidewall during the subsequent etch process. Imperfections in sidewall smoothness (that is, sidewall roughness) can potentially reduce die strength, and can also provide a cosmetic issue that affects market penetration of the resulting product. Since the ablation threshold of each material is different, applying a laser beam of constant irradiation fluence inevitably causes different ablation spot size at different locations when material and/or pattern geometry varies. Process optimization may reduce the kerf width variation to some extent but total elimination can be difficult.

In accordance with an embodiment of the present invention, a combination of an elliptical profile laser beam laser scribing process with a plasma etching process, or a combination of a spatio-temporal controlled profile laser beam laser scribing process, may be used to dice a semiconductor wafer into singulated integrated circuits. FIG. 1A is a Flowchart 100A representing operations in a method of dicing a semiconductor wafer including a plurality of integrated circuits, in accordance with an embodiment of the present invention. FIG. 1B is a Flowchart 100B representing operations in another method of dicing a semiconductor wafer including a plurality of integrated circuits, in accordance with another embodiment of the present invention. FIGS. 2A-2C illustrate cross-sectional views of a semiconductor wafer including a plurality of integrated circuits during performing of a method of dicing the semiconductor wafer, corresponding to operations of Flowchart 100A or 100B.

Referring to operation 102A of Flowchart 100A or to operation 102B of Flowchart 100B, and corresponding FIG. 2A, a mask 202 is formed above a semiconductor wafer or substrate 204. The mask 202 is composed of a layer covering and protecting integrated circuits 206 formed on the surface of semiconductor wafer 204. The mask 202 also covers intervening streets 207 formed between each of the integrated circuits 206.

In accordance with an embodiment of the present invention, forming the mask 202 includes forming a layer such as, but not limited to, a photo-resist layer or an I-line patterning layer. For example, a polymer layer such as a photo-resist layer may be composed of a material otherwise suitable for use in a lithographic process. In one embodiment, the photo-resist layer is composed of a positive photo-resist material such as, but not limited to, a 248 nanometer (nm) resist, a 193 nm resist, a 157 nm resist, an extreme ultra-violet (EUV) resist, or a phenolic resin matrix with a diazonaphthoquinone sensitizer. In another embodiment, the photo-resist layer is composed of a negative photo-resist material such as, but not limited to, poly-cis-isoprene and poly-vinyl-cinnamate.

In another embodiment, forming the mask 202 involves forming a layer deposited in a plasma deposition process. For example, in one such embodiment, the mask 202 is composed of a plasma deposited Teflon or Teflon-like (polymeric CF₂) layer. In a specific embodiment, the polymeric CF₂ layer is deposited in a plasma deposition process involving the gas C₄F₈.

In another embodiment, forming the mask 202 involves forming a water-soluble mask layer. In an embodiment, the water-soluble mask layer is readily dissolvable in an aqueous media. For example, in one embodiment, the water-soluble mask layer is composed of a material that is soluble in one or more of an alkaline solution, an acidic solution, or in deionized water. In an embodiment, the water-soluble mask layer maintains its water solubility upon exposure to a heating process, such as heating approximately in the range of 50-160 degrees Celsius. For example, in one embodiment, the water-soluble mask layer is soluble in aqueous solutions following exposure to chamber conditions used in a laser and plasma etch singulation process. In one embodiment, the water-soluble mask layer is composed of a material such as, but not limited to, polyvinyl alcohol, polyacrylic acid, dextran, polymethacrylic acid, polyethylene imine, or polyethylene oxide. In a specific embodiment, the water-soluble mask layer has an etch rate in an aqueous solution approximately in the range of 1-15 microns per minute and, more particularly, approximately 1.3 microns per minute.

In another embodiment, forming the mask 202 involves forming a UV-curable mask layer. In an embodiment, the mask layer has a susceptibility to UV light that reduces an adhesiveness of the UV-curable layer by at least approximately 80%. In one such embodiment, the UV layer is composed of polyvinyl chloride or an acrylic-based material. In an embodiment, the UV-curable layer is composed of a material or stack of materials with an adhesive property that weakens upon exposure to UV light. In an embodiment, the UV-curable adhesive film is sensitive to approximately 365 nm UV light. In one such embodiment, this sensitivity enables use of LED light to perform a cure.

In an embodiment, semiconductor wafer or substrate 204 is composed of a material suitable to withstand a fabrication process and upon which semiconductor processing layers may suitably be disposed. For example, in one embodiment, semiconductor wafer or substrate 204 is composed of a group IV-based material such as, but not limited to, crystalline silicon, germanium or silicon/germanium. In a specific embodiment, providing semiconductor wafer 204 includes providing a monocrystalline silicon substrate. In a particular embodiment, the monocrystalline silicon substrate is doped with impurity atoms. In another embodiment, semiconductor wafer or substrate 204 is composed of a III-V material such as, e.g., a III-V material substrate used in the fabrication of light emitting diodes (LEDs).

In an embodiment, semiconductor wafer or substrate 204 has disposed thereon or therein, as a portion of the integrated circuits 206, an array of semiconductor devices. Examples of such semiconductor devices include, but are not limited to, memory devices or complimentary metal-oxide-semiconductor (CMOS) transistors fabricated in a silicon substrate and encased in a dielectric layer. A plurality of metal interconnects may be formed above the devices or transistors, and in surrounding dielectric layers, and may be used to electrically couple the devices or transistors to form the integrated circuits 206. Materials making up the streets 207 may be similar to or the same as those materials used to form the integrated circuits 206. For example, streets 207 may be composed of layers of dielectric materials, semiconductor materials, and metallization. In one embodiment, one or more of the streets 207 includes test devices similar to the actual devices of the integrated circuits 206.

In a first particular embodiment, referring to operation 104A of Flowchart 100A, and corresponding FIG. 2B, the mask 202 is patterned with an elliptical profile laser beam laser scribing process to provide a patterned mask 208 with gaps 210, exposing regions of the semiconductor wafer or substrate 204 between the integrated circuits 206. As such, the elliptical profile based laser scribing process is used to remove the material of the streets 207 originally formed between the integrated circuits 206. In accordance with an embodiment of the present invention, patterning the mask 202 with the elliptical profile laser beam laser scribing process includes forming trenches 212 partially into the regions of the semiconductor wafer 204 between the integrated circuits 206, as depicted in FIG. 2B.

FIG. 3A illustrates two possible pathways for elliptical beam profile generation, in accordance with an embodiment of the present invention. Referring to pathway (i) of FIG. 3A, an input beam 302, such as a Gaussian beam, is transmitted through a cylindrical lens 304. An elliptical beam 306 is output from the cylindrical lens 304. Referring to pathway (ii) of FIG. 3A, an input beam 312, such as a Gaussian beam, is transmitted through a cylindrical lens 314. The output beam is subjected to beam collimation optics 315. An elliptical beam 316 is output from the cylindrical lens beam collimation optics 315. The elliptical beam 316, as compared to the elliptical beam 306, has a longer depth of focus as a result of passing through the beam collimation optics 315. In both cases of pathway (i) or pathway (ii), the use of a cylindrical lens (304 or 314) generates an elliptical laser beam 306 or 316, respectively, and smoothens out the scribed pattern when compared with a circular beam process.

FIG. 3B illustrates possible orientation of a generated elliptical beam, in accordance with an embodiment of the present invention. Referring to orientation (i) of FIG. 3B, a laser beam 322 having a vertically orientated elliptical profile is generated. Referring to orientation (ii) of FIG. 3B, a laser beam 324 having a horizontally orientated elliptical profile is generated. Referring to orientation (iii) of FIG. 3B, a laser beam 326 having a clock-wise tilted orientation elliptical profile is generated. Referring to orientation (iv) of FIG. 3B, a laser beam 328 having a counter clock-wise tilted orientation elliptical profile is generated. In all instances (i)-(iv), in an embodiment, the position of cylindrical lens determines the generated elliptical beam orientation. In an embodiment, regardless of orientation, the resulting elliptical beam has a long (major) axis at least twice the length of the corresponding short (minor) axis. In a particular embodiment, regardless of orientation, the resulting elliptical beam has a long (major) axis at least four times the length of the corresponding short (minor) axis.

FIG. 3C illustrates a comparison of scribing roughness for (i) a circular beam process versus (ii) an elliptical beam process, in accordance with an embodiment of the present invention. Referring to laser scribing process (i) of FIG. 3C, a plurality of circular beam spots 332 is overlapped to provide a scribing profile 334. The scribing profile 334 has a non-liner or bumpy profile due to indentations 336 where circular portions overlap. By contrast, referring to laser scribing process (ii) of FIG. 3C, a plurality of elliptical beam spots 338 is overlapped to provide a scribing profile 340. The scribing profile 340 has an essentially liner profile where elliptical portions overlap. In comparing scribing processes (i) and (ii), a scribing process (ii) can be improved by a reduction or elimination of scribing roughness, which is otherwise observed in scribing process (i) based on circular beam spots.

In a second particular embodiment, referring to operation 104B of Flowchart 100B, and corresponding FIG. 2B, the mask 202 is patterned with a spatio-temporal controlled profile laser beam laser scribing process to provide a patterned mask 208 with gaps 210, exposing regions of the semiconductor wafer or substrate 204 between the integrated circuits 206. As such, the spatio-temporal controlled profile based laser scribing process is used to remove the material of the streets 207 originally formed between the integrated circuits 206. In accordance with an embodiment of the present invention, patterning the mask 202 with the spatio-temporal controlled profile laser beam laser scribing process includes forming trenches 212 partially into the regions of the semiconductor wafer 204 between the integrated circuits 206, as depicted in FIG. 2B.

FIG. 4A illustrates a comparison of scribing roughness for (i) a circular beam process versus (ii) a flat-top beam process or (iii) an elliptical beam process, in accordance with an embodiment of the present invention. Referring to laser scribing process (i) of FIG. 4A, a plurality of circular beam spots 402 is overlapped to provide a scribing profile 404. The scribing profile 404 has a non-liner or bumpy profile due to indentations 406 where circular portions overlap. By contrast, referring to laser scribing process (ii) of FIG. 4A, a plurality of flat-top beam spots 408 is overlapped to provide a scribing profile 410. The scribing profile 410 has an essentially liner profile where flat-top portions overlap. Referring to laser scribing process (iii) of FIG. 4A, a plurality of elliptical beam spots 412 is overlapped to provide a scribing profile 414. The scribing profile 414 has an essentially liner profile where elliptical portions overlap. In comparing scribing processes (i) versus (ii) and (iii), a scribing process (ii) or (iii) can be improved by a reduction or elimination of scribing roughness, which is otherwise observed in scribing process (i) based on circular beam spots. In an embodiment, fine roughness is thus achieved by spatial laser beam control.

FIG. 4B illustrates sidewall finishing for (i) a femtosecond laser, (ii) a picosecond laser and (iii) a temporally controlled laser, in accordance with an embodiment of the present invention. Referring to FIG. 4B, an angled cross-sectional view of a sidewall of a silicon substrate scribed by a femtosecond laser ((i), sidewall 420), a picosecond laser ((ii), sidewall 422), and a temporally controlled laser ((iii), sidewall 424). In an embodiment, the temporally-controlled laser scribing process involves scribing with a laser beam having a profile including a leading femto-second portion and a trailing lower-intensity, higher fluence portion. In one such embodiment, the trailing lower-intensity, higher fluence portion is a second femto-second portion longer than the leading femto-second portion. For example, in a specific embodiment, the leading femtosecond portion is approximately in the range of 10-300 femtoseconds, while the trailing portion is approximately in the range of 300 to 999 femtoseconds. In another embodiment, the trailing lower-intensity, higher fluence portion is a pico-second portion.

FIG. 4C illustrates a laser scribing process including generation of a spatio-temporally controlled laser, in accordance with an embodiments of the present invention. Referring to FIG. 4C, at operation 432, initial sourcing of a laser beam is provided by a femtosecond laser oscillator. At operation 434, the resulting femtosecond laser from operation 432 is subjected to a laser pulse shaper for temporal control of the beam pulse. At operation 436, the resulting temporally shaped laser beam from operation 434 is subjected to a spatial profile modulator (e.g., to form an elliptical or flat-top shape). At operation 438, a laser beam subjected to both temporal and spatial control is ultimately applied in a wafer scribing process.

As described above, in an embodiment, a femtosecond-based laser is used as a source for an elliptical profile laser beam laser scribing process or a spatio-temporal controlled profile laser beam laser scribing process. For example, in an embodiment, a laser with a wavelength in the visible spectrum plus the ultra-violet (UV) and infra-red (IR) ranges (totaling a broadband optical spectrum) is used to provide a femtosecond-based laser, i.e., a laser with a pulse width on the order of the femtosecond (10⁻¹⁵ seconds). In one embodiment, ablation is not, or is essentially not, wavelength dependent and is thus suitable for complex films such as films of the mask 202, the streets 207 and, possibly, a portion of the semiconductor wafer or substrate 204.

FIG. 5 illustrates the effects of using a laser pulse width in the femtosecond range, picosecond range, and nanosecond range, in accordance with an embodiment of the present invention. Referring to FIG. 5, by using a laser beam profile with contributions from the femtosecond range, heat damage issues are mitigated or eliminated (e.g., minimal to no damage 502C with femtosecond processing of a via 500C) versus longer pulse widths (e.g., significant damage 502A with nanosecond processing of a via 500A). The elimination or mitigation of damage during formation of via 500C may be due to a lack of low energy recoupling (as is seen for picosecond-based laser ablation of 500B/502B) or thermal equilibrium (as is seen for nanosecond-based laser ablation), as depicted in FIG. 5.

Laser parameters selection, such as beam profile, may be critical to developing a successful laser scribing and dicing process that minimizes chipping, microcracks and delamination in order to achieve clean laser scribe cuts. The cleaner the laser scribe cut, the smoother an etch process that may be performed for ultimate die singulation. In semiconductor device wafers, many functional layers of different material types (e.g., conductors, insulators, semiconductors) and thicknesses are typically disposed thereon. Such materials may include, but are not limited to, organic materials such as polymers, metals, or inorganic dielectrics such as silicon dioxide and silicon nitride.

A street between individual integrated circuits disposed on a wafer or substrate may include the similar or same layers as the integrated circuits themselves. For example, FIG. 6 illustrates a cross-sectional view of a stack of materials that may be used in a street region of a semiconductor wafer or substrate, in accordance with an embodiment of the present invention.

Referring to FIG. 6, a street region 600 includes the top portion 602 of a silicon substrate, a first silicon dioxide layer 604, a first etch stop layer 606, a first low K dielectric layer 608 (e.g., having a dielectric constant of less than the dielectric constant of 4.0 for silicon dioxide), a second etch stop layer 610, a second low K dielectric layer 612, a third etch stop layer 614, an undoped silica glass (USG) layer 616, a second silicon dioxide layer 618, and a layer of photo-resist 620, with relative thicknesses depicted. Copper metallization 622 is disposed between the first and third etch stop layers 606 and 614 and through the second etch stop layer 610. In a specific embodiment, the first, second and third etch stop layers 606, 610 and 614 are composed of silicon nitride, while low K dielectric layers 608 and 612 are composed of a carbon-doped silicon oxide material.

Under conventional laser irradiation (such as nanosecond-based irradiation), the materials of street 600 behave quite differently in terms of optical absorption and ablation mechanisms. For example, dielectrics layers such as silicon dioxide, is essentially transparent to all commercially available laser wavelengths under normal conditions. By contrast, metals, organics (e.g., low K materials) and silicon can couple photons very easily, particularly in response to nanosecond-based irradiation. In an embodiment, an elliptical profile laser beam laser scribing process or a spatio-temporal controlled profile laser beam laser scribing process is used to pattern a layer of silicon dioxide, a layer of low K material, and a layer of copper by ablating the layer of silicon dioxide prior to ablating the layer of low K material and the layer of copper.

In case that the elliptical profile laser beam or the spatio-temporal controlled profile laser beam is a femtosecond-based laser beam, in an embodiment, suitable femtosecond-based laser processes are characterized by a high peak intensity (irradiance) that usually leads to nonlinear interactions in various materials. In one such embodiment, the femtosecond laser sources have a pulse width approximately in the range of 10 femtoseconds to 500 femtoseconds, although preferably in the range of 100 femtoseconds to 400 femtoseconds. In one embodiment, the femtosecond laser sources have a wavelength approximately in the range of 1570 nanometers to 200 nanometers, although preferably in the range of 540 nanometers to 250 nanometers. In one embodiment, the laser and corresponding optical system provide a focal spot at the work surface approximately in the range of 3 microns to 15 microns, though preferably approximately in the range of 5 microns to 10 microns or between 10-15 microns.

In an embodiment, the laser source has a pulse repetition rate approximately in the range of 200 kHz to 10 MHz, although preferably approximately in the range of 500 kHz to 5 MHz. In an embodiment, the laser source delivers pulse energy at the work surface approximately in the range of 0.5 uJ to 100 uJ, although preferably approximately in the range of 1 uJ to 5 uJ. In an embodiment, the laser scribing process runs along a work piece surface at a speed approximately in the range of 500 mm/sec to 5 m/sec, although preferably approximately in the range of 600 mm/sec to 2 m/sec.

The scribing process may be run in single pass only, or in multiple passes, but, in an embodiment, preferably 1-2 passes. In one embodiment, the scribing depth in the work piece is approximately in the range of 5 microns to 50 microns deep, preferably approximately in the range of 10 microns to 20 microns deep. In an embodiment, the kerf width of the laser beam generated is approximately in the range of 2 microns to 30 microns, although in silicon wafer scribing/dicing preferably approximately in the range of 6 microns to 20 microns, measured at the device/silicon interface.

Laser parameters may be selected with benefits and advantages such as providing sufficiently high laser intensity to achieve ionization of inorganic dielectrics (e.g., silicon dioxide) and to minimize delamination and chipping caused by underlayer damage prior to direct ablation of inorganic dielectrics. Also, parameters may be selected to provide meaningful process throughput for industrial applications with precisely controlled ablation width (e.g., kerf width) and depth. In an embodiment, an elliptical profile laser beam laser scribing process is suitable to provide such advantages. In another embodiment, a spatio-temporal controlled profile laser beam laser scribing process is suitable to provide such advantages.

It is to be appreciated that the dicing or singulation process could be stopped after the above described laser scribing in a case that the laser scribing is used to pattern the mask as well as to scribe fully through the wafer or substrate in order to singulate the dies. Accordingly, further singulation processing would not be required in such a case. However, the following embodiments may be considered in cases where laser scribing alone is not implemented for total singulation.

Referring now to optional operation 106A of Flowchart 100A or to optional operation 106B of Flowchart 100B, an intermediate post mask-opening cleaning operation is performed. In an embodiment, the post mask-opening cleaning operation is a plasma-based cleaning process. In a first example, as described below, the plasma-based cleaning process is reactive to the regions of the substrate 204 exposed by the gaps 210. In the case of a reactive plasma-based cleaning process, the cleaning process itself may form or extend trenches 212 in the substrate 204 since the reactive plasma-based cleaning operation is at least somewhat of an etchant for the substrate 204. In a second, different, example, as is also described below, the plasma-based cleaning process is non-reactive to the regions of the substrate 204 exposed by the gaps 210.

In accordance with a first embodiment, the plasma-based cleaning process is reactive to exposed regions of the substrate 204 in that the exposed regions are partially etched during the cleaning process. In one such embodiment, Ar or another non-reactive gas (or the mix) is combined with SF₆ for a highly-biased plasma treatment for cleaning of scribed openings. The plasma treatment using mixed gases Ar+SF₆ under high-bias power is performed for bombarding mask-opened regions to achieve cleaning of the mask-opened regions. In the reactive breakthrough process, both physical bombardment from Ar and SF₆ along with chemical etching due to SF₆ and F-ions contribute to cleaning of mask-opened regions. The approach may be suitable for photoresist or plasma-deposited Teflon masks 202, where breakthrough treatment leads to fairly uniform mask thickness reduction and a gentle Si etch. Such a breakthrough etch process, however, may not be best suited for water soluble mask materials.

In accordance with a second embodiment, the plasma-based cleaning process is non-reactive to exposed regions of the substrate 204 in that the exposed regions are not or only negligible etched during the cleaning process. In one such embodiment, only non-reactive gas plasma cleaning is used. For example, Ar or another non-reactive gas (or the mix) is used to perform a highly-biased plasma treatment both for mask condensation and cleaning of scribed openings. The approach may be suitable for water-soluble masks or for thinner plasma-deposited Teflon 202. In another such embodiment, separate mask condensation and scribed trench cleaning operations are used, e.g., an Ar or non-reactive gas (or the mix) highly-biased plasma treatment for mask condensation is first performed, and then an Ar+SF₆ plasma cleaning of a laser scribed trench is performed. This embodiment may be suitable for cases where Ar-cleaning is not sufficient for trench cleaning due to too thick of a mask material. Cleaning efficiency is improved for thinner masks, but mask etch rate is much lower, with almost no consumption in a subsequent deep silicon etch process. In yet another such embodiment, three-operation cleaning is performed: (a) Ar or non-reactive gas (or the mix) highly-biased plasma treatment for mask condensation, (b) Ar+SF₆ highly-biased plasma cleaning of laser scribed trenches, and (c) Ar or non-reactive gas (or the mix) highly-biased plasma treatment for mask condensation. In accordance with another embodiment of the present invention, a plasma cleaning operation involves first use of a reactive plasma cleaning treatment, such as described above in the first aspect of operation 106. The reactive plasma cleaning treatment is then followed by a non-reactive plasma cleaning treatment such as described in association with the second aspect of operation 106.

Referring to operation 108A of Flowchart 100A or to operation 108B of Flowchart 100B, and corresponding FIG. 2C, the semiconductor wafer 204 is etched through the gaps 210 in the patterned mask 208 to singulate the integrated circuits 206. In accordance with an embodiment of the present invention, etching the semiconductor wafer 204 includes ultimately etching entirely through semiconductor wafer 204, as depicted in FIG. 2C, by etching the trenches 212 initially formed with the elliptical profile laser beam laser scribing process or the spatio-temporal controlled profile laser beam laser scribing process.

In accordance with an embodiment of the present invention, the resulting roughness of mask opening from laser scribing can impact die sidewall quality resulting from the subsequent formation of a plasma etched trench. Lithographically opened masks often have smooth profiles, leading to smooth corresponding sidewalls of a plasma etched trench. By contrast, a conventional laser opened mask can have a very rough profile along a scribing direction if improper laser process parameters are selected (such as spot overlap, leading to rough sidewall of plasma etched trench horizontally). Although the surface roughness can be smoothened by additional plasma processes, there is a cost and throughput hit to remedying such issues. Accordingly, embodiments described herein may be advantageous in providing a smoother scribing process from the laser scribing portion of the singulation process.

In an embodiment, etching the semiconductor wafer 204 includes using a plasma etching process. In one embodiment, a through-silicon via type etch process is used. For example, in a specific embodiment, the etch rate of the material of semiconductor wafer 204 is greater than 25 microns per minute. An ultra-high-density plasma source may be used for the plasma etching portion of the die singulation process. An example of a process chamber suitable to perform such a plasma etch process is the Applied Centura® Silvia™ Etch system available from Applied Materials of Sunnyvale, Calif., USA. The Applied Centura® Silvia™ Etch system combines the capacitive and inductive RF coupling, which gives much more independent control of the ion density and ion energy than was possible with the capacitive coupling only, even with the improvements provided by magnetic enhancement. This combination enables effective decoupling of the ion density from ion energy, so as to achieve relatively high density plasmas without the high, potentially damaging, DC bias levels, even at very low pressures. This results in an exceptionally wide process window. However, any plasma etch chamber capable of etching silicon may be used. In an exemplary embodiment, a deep silicon etch is used to etch a single crystalline silicon substrate or wafer 204 at an etch rate greater than approximately 40% of conventional silicon etch rates while maintaining essentially precise profile control and virtually scallop-free sidewalls. In a specific embodiment, a through-silicon via type etch process is used. The etch process is based on a plasma generated from a reactive gas, which generally a fluorine-based gas such as SF₆, C₄F₈, CHF₃, XeF₂, or any other reactant gas capable of etching silicon at a relatively fast etch rate. In an embodiment, the mask layer 208 is removed after the singulation process, as depicted in FIG. 2C. In another embodiment, the plasma etching operation described in association with FIG. 2C employs a conventional Bosch-type dep/etch/dep process to etch through the substrate 204. Generally, a Bosch-type process consists of three sub-operations: deposition, a directional bombardment etch, and isotropic chemical etch which is run through many iterations (cycles) until silicon is etched through.

Accordingly, referring again to Flowchart 100A, Flowchart 100B, and FIGS. 2A-2C, wafer dicing may be preformed by initial ablation using an elliptical profile laser beam laser scribing process or a spatio-temporal controlled profile laser beam laser scribing process to ablate through a mask layer, through wafer streets (including metallization), and partially into a silicon substrate. Die singulation may then be completed by subsequent through-silicon deep plasma etching. A specific example of a materials stack for dicing is described below in association with FIGS. 7A-7D, in accordance with an embodiment of the present invention.

Referring to FIG. 7A, a materials stack for hybrid laser ablation and plasma etch dicing includes a mask layer 702, a device layer 704, and a substrate 706. The mask layer, device layer, and substrate are disposed above a die attach film 708 which is affixed to a backing tape 710. In an embodiment, the mask layer 702 is a water soluble layer such as the water soluble layers described above in association with mask 202. The device layer 704 includes an inorganic dielectric layer (such as silicon dioxide) disposed above one or more metal layers (such as copper layers) and one or more low K dielectric layers (such as carbon-doped oxide layers). The device layer 704 also includes streets arranged between integrated circuits, the streets including the same or similar layers to the integrated circuits. The substrate 706 is a bulk single-crystalline silicon substrate.

In an embodiment, the bulk single-crystalline silicon substrate 706 is thinned from the backside prior to being affixed to the die attach film 708. The thinning may be performed by a backside grind process. In one embodiment, the bulk single-crystalline silicon substrate 706 is thinned to a thickness approximately in the range of 50-100 microns. It is important to note that, in an embodiment, the thinning is performed prior to a laser ablation and plasma etch dicing process. In an embodiment, the photo-resist layer 702 has a thickness of approximately 5 microns and the device layer 704 has a thickness approximately in the range of 2-3 microns. In an embodiment, the die attach film 708 (or any suitable substitute capable of bonding a thinned or thin wafer or substrate to the backing tape 710) has a thickness of approximately 20 microns.

Referring to FIG. 7B, the mask 702, the device layer 704 and a portion of the substrate 706 are patterned with an elliptical profile laser beam laser scribing process or a spatio-temporal controlled profile laser beam laser scribing process 712 to form trenches 714 in the substrate 706. Referring to FIG. 7C, a through-silicon deep plasma etch process 716 is used to extend the trench 714 down to the die attach film 708, exposing the top portion of the die attach film 708 and singulating the silicon substrate 706. The device layer 704 is protected by the mask layer 702 during the through-silicon deep plasma etch process 716.

Referring to FIG. 7D, the singulation process may further include patterning the die attach film 708, exposing the top portion of the backing tape 710 and singulating the die attach film 708. In an embodiment, the die attach film is singulated by a laser process or by an etch process. Further embodiments may include subsequently removing the singulated portions of substrate 706 (e.g., as individual integrated circuits) from the backing tape 710. In one embodiment, the singulated die attach film 708 is retained on the back sides of the singulated portions of substrate 706. Other embodiments may include removing the mask layer 702 from the device layer 704. In an alternative embodiment, in the case that substrate 706 is thinner than approximately 50 microns, the elliptical profile or spatio-temporal controlled profile laser beam laser scribing process 712 is used to completely singulate substrate 706 without the use of an additional plasma process.

A single process tool may be configured to perform many or all of the operations in a hybrid ablation and plasma etch singulation process based on an elliptical profile laser beam laser scribing process or a spatio-temporal controlled profile laser beam laser scribing process. For example, FIG. 8 illustrates a block diagram of a tool layout for laser and plasma dicing of wafers or substrates, in accordance with an embodiment of the present invention.

Referring to FIG. 8, a process tool 800 includes a factory interface 802 (FI) having a plurality of load locks 804 coupled therewith. A cluster tool 806 is coupled with the factory interface 802. The cluster tool 806 includes one or more plasma etch chambers, such as plasma etch chamber 808. A laser scribe apparatus 810 is also coupled to the factory interface 802. The overall footprint of the process tool 800 may be, in one embodiment, approximately 3500 millimeters (3.5 meters) by approximately 3800 millimeters (3.8 meters), as depicted in FIG. 8.

In an embodiment, the laser scribe apparatus 810 houses a laser assembly configured to provide a laser beam having an elliptical profile or a spatio-temporal controlled profile. In a first such embodiment, the laser assembly is configured to provide the laser beam having an elliptical profile. In a particular such embodiment, the laser assembly includes a cylindrical lens. In an embodiment, the laser assembly further includes beam collimating optics. In an embodiment, the laser assembly is configured to generate a femtosecond-based laser beam from a femtosecond oscillator.

In a second such embodiment, the laser assembly is configured to provide the laser beam having a spatio-temporal controlled profile. In a particular such embodiment, the laser assembly includes a laser pulse shaper and a spatial profile modulator. In an embodiment, the laser assembly is configured to generate a femtosecond-based laser beam from a femtosecond oscillator.

In an embodiment, the laser is suitable for performing a laser ablation portion of a hybrid laser and etch singulation process, such as the laser ablation processes described above. In one embodiment, a moveable stage is also included in laser scribe apparatus 810, the moveable stage configured for moving a wafer or substrate (or a carrier thereof) relative to the laser. In a specific embodiment, the laser is also moveable. The overall footprint of the laser scribe apparatus 810 may be, in one embodiment, approximately 2240 millimeters by approximately 1270 millimeters, as depicted in FIG. 8.

In an embodiment, the one or more plasma etch chambers 808 is configured for etching a wafer or substrate through the gaps in a patterned mask to singulate a plurality of integrated circuits. In one such embodiment, the one or more plasma etch chambers 808 is configured to perform a deep silicon etch process. In a specific embodiment, the one or more plasma etch chambers 808 is an Applied Centura® Silvia™ Etch system, available from Applied Materials of Sunnyvale, Calif., USA. The etch chamber may be specifically designed for a deep silicon etch used to create singulate integrated circuits housed on or in single crystalline silicon substrates or wafers. In an embodiment, a high-density plasma source is included in the plasma etch chamber 808 to facilitate high silicon etch rates. In an embodiment, more than one etch chamber is included in the cluster tool 806 portion of process tool 800 to enable high manufacturing throughput of the singulation or dicing process.

The factory interface 802 may be a suitable atmospheric port to interface between an outside manufacturing facility with laser scribe apparatus 810 and cluster tool 806. The factory interface 802 may include robots with arms or blades for transferring wafers (or carriers thereof) from storage units (such as front opening unified pods) into either cluster tool 806 or laser scribe apparatus 810, or both.

Cluster tool 806 may include other chambers suitable for performing functions in a method of singulation. For example, in one embodiment, in place of an additional etch chamber, a deposition chamber 812 is included. The deposition chamber 812 may be configured for mask deposition on or above a device layer of a wafer or substrate prior to laser scribing of the wafer or substrate. In one such embodiment, the deposition chamber 812 is suitable for depositing a photo-resist layer. In another embodiment, in place of an additional etch chamber, a wet/dry station 814 is included. The wet/dry station may be suitable for cleaning residues and fragments, or for removing a mask, subsequent to a laser scribe and plasma etch singulation process of a substrate or wafer. In yet another embodiment, in place of an additional deep silicon etch chamber, a plasma etch chamber is included and is configured for performing a plasma-based cleaning process. In an embodiment, a metrology station is also included as a component of process tool 800.

Embodiments of the present invention may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to embodiments of the present invention. In one embodiment, the computer system is coupled with process tool 800 described in association with FIG. 8. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (electrical, optical, acoustical or other form of propagated signals (e.g., infrared signals, digital signals, etc.)), etc.

FIG. 9 illustrates a diagrammatic representation of a machine in the exemplary form of a computer system 900 within which a set of instructions, for causing the machine to perform any one or more of the methodologies described herein, may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a Local Area Network (LAN), an intranet, an extranet, or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies described herein.

The exemplary computer system 900 includes a processor 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory 918 (e.g., a data storage device), which communicate with each other via a bus 930.

Processor 902 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processor 902 may be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processor 902 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. Processor 902 is configured to execute the processing logic 926 for performing the operations described herein.

The computer system 900 may further include a network interface device 908. The computer system 900 also may include a video display unit 910 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., a mouse), and a signal generation device 916 (e.g., a speaker).

The secondary memory 918 may include a machine-accessible storage medium (or more specifically a computer-readable storage medium) 932 on which is stored one or more sets of instructions (e.g., software 922) embodying any one or more of the methodologies or functions described herein. The software 922 may also reside, completely or at least partially, within the main memory 904 and/or within the processor 902 during execution thereof by the computer system 900, the main memory 904 and the processor 902 also constituting machine-readable storage media. The software 922 may further be transmitted or received over a network 920 via the network interface device 908.

While the machine-accessible storage medium 932 is shown in an exemplary embodiment to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present invention. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.

In accordance with an embodiment of the present invention, a machine-accessible storage medium has instructions stored thereon which cause a data processing system to perform a method of dicing a semiconductor wafer having a plurality of integrated circuits. The method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an elliptical or a spatio-temporal controlled laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Thus, hybrid wafer dicing approaches using an elliptical or a spatio-temporal controlled laser beam profile laser scribing process and plasma etch process have been disclosed. 

What is claimed is:
 1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising: forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits; patterning the mask with an elliptical laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits, wherein a major axis of an elliptical beam of the elliptical laser beam profile laser scribing process is oriented off of the direction of travel of the elliptical beam; and plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.
 2. The method of claim 1, wherein patterning the mask with the elliptical laser beam profile laser scribing process comprises generating a laser beam and passing the beam through a cylindrical lens prior to impinging the laser beam on the mask.
 3. The method of claim 2, wherein, subsequent to passing the laser beam through the cylindrical lens and prior to impinging the laser beam on the mask, the laser beam is further passed through beam collimation optics.
 4. The method of claim 2, wherein generating the laser beam comprises generating a femtosecond-based laser beam.
 5. The method of claim 1, wherein patterning the mask with the laser scribing process comprises forming trenches in the regions of the semiconductor wafer between the integrated circuits, and wherein plasma etching the semiconductor wafer comprises extending the trenches to form corresponding trench extensions.
 6. The method of claim 5, wherein each of the trenches has a width, and wherein each of the corresponding trench extensions has the width.
 7. The method of claim 1, further comprising: subsequent to patterning the mask with the elliptical laser beam profile laser scribing process and prior to plasma etching the semiconductor wafer through the gaps, cleaning the exposed regions of the semiconductor wafer with a plasma process.
 8. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising: forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits; patterning the mask with a spatio-temporal controlled laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits; plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits; and subsequent to patterning the mask with the spatio-temporal controlled laser beam profile laser scribing process and prior to plasma etching the semiconductor wafer through the gaps, cleaning the exposed regions of the semiconductor wafer with a plasma process.
 9. The method of claim 8, wherein patterning the mask with the spatio-temporal controlled laser beam profile laser scribing process comprises generating a laser beam and passing the laser beam first through a laser pulse shaper for beam pulse temporal control and then through a spatial profile modulator prior to impinging the laser beam on the mask.
 10. The method of claim 9, wherein passing the laser beam through the spatial profile modulator comprises forming an elliptical shaped laser beam or a flat-top shaped laser beam.
 11. The method of claim 9, wherein generating the laser beam comprises generating a femtosecond-based laser beam.
 12. The method of claim 8, wherein patterning the mask with the laser scribing process comprises forming trenches in the regions of the semiconductor wafer between the integrated circuits, and wherein plasma etching the semiconductor wafer comprises extending the trenches to form corresponding trench extensions.
 13. The method of claim 12, wherein each of the trenches has a width, and wherein each of the corresponding trench extensions has the width.
 14. The method of claim 8, wherein cleaning the exposed regions of the semiconductor wafer with the plasma process comprises using a reactive plasma-based cleaning process.
 15. The method of claim 8, wherein cleaning the exposed regions of the semiconductor wafer with the plasma process comprises using a non-reactive plasma-based cleaning process.
 16. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising: forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits; patterning the mask with an elliptical laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits; plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits; and subsequent to patterning the mask with the elliptical laser beam profile laser scribing process and prior to plasma etching the semiconductor wafer through the gaps, cleaning the exposed regions of the semiconductor wafer with a plasma process.
 17. The method of claim 16, wherein patterning the mask with the elliptical laser beam profile laser scribing process comprises generating a laser beam and passing the beam through a cylindrical lens prior to impinging the laser beam on the mask.
 18. The method of claim 17, wherein, subsequent to passing the laser beam through the cylindrical lens and prior to impinging the laser beam on the mask, the laser beam is further passed through beam collimation optics.
 19. The method of claim 16, wherein cleaning the exposed regions of the semiconductor wafer with the plasma process comprises using a reactive plasma-based cleaning process.
 20. The method of claim 16, wherein cleaning the exposed regions of the semiconductor wafer with the plasma process comprises using a non-reactive plasma-based cleaning process. 